On chip debugging method of microcontrollers

ABSTRACT

A microcontroller includes an external interface terminal group, a data transmit/receive section, and a DMA controller comprised of an address register for storing therein an address of a hardware serving as an object to be accessed by DMA, registers for executing read/write by the DMA, a control flag for controlling the start of the DMA, and a timing controller of the DMA. The microcontroller further includes a register for storing therein flag information for determining whether access can be executed or not by the DMA and a unit for outputting a bus state recognition signal indicating whether a bus state is rendered in a state to be accessed or not by the DMA.

FIELD OF THE INVENTION

The present invention relates to an on-chip debugging method(hereinafter referred to as a RAM monitor) which is capable of debuggingand tuning a microcontroller unit (hereinafter referred to as a MCU) ina state implemented on a chip.

BACKGROUND OF THE INVENTION

The latest one chip MCU frequently has a RAM monitor function fordebugging and tuning an internal program of the MCU in a stateimplemented on a chip (hereinafter referred to as MCU 100 with abuilt-in RAM monitor or simply referred to as MCU 100). FIG. 1 shows theconfiguration of a conventional MCU 100.

The RAM monitor function can be realized when the MCU 100 receives anexternal clock and external data and outputs data by way of an externalinterface terminal group 102.

The conventional MCU 100 comprises an external interface terminal group102, a data transmit/receive section 104, a direct memory access controlcircuit (hereinafter referred to as DMA controller) 110, and alsocomprises a CPU 120, a ROM 130, a RAM 140, a peripheral module 1 (150)and a peripheral module 2 (160) respectively connected with one anotherby way of an internal bus formed of a data bus (DBUS) 106 and an addressbus (ABUS) 108.

The DMA controller 110 comprises a GO flag set F/F 111, an AND gate 115,an address register (AReg) 112, a data write register (WReg) 113, a dataread register (RReg) 114, and a timing controller 116.

The GO flag set F/F 111 is set upon completion of reception of anaddress/data from the transmit/receive section 104 and reset uponcompletion of a DMA transfer operation. An output signal from the GOflag set F/F 111 is inputted to the AND gate 115 together with a busstate recognition signal 101 and generates a DMA start signal 124. Thebus state recognition signal 101 is a signal which takes aninsignificant value (e.g. “0”) when the CPU 120 occupies the bus and theDMA is placed in a bus use prohibition state, and which takes asignificant value (e.g. “1”) when the CPU 120 releases the bus and theDMA is placed in a bus use permission state.

Further, the timing controller 116 executes write/read relative to theregisters, the RAM and the like by the DMA operation at a given timingat the time when a GO flag is set by the GO flag set F/F 111 and the busstate recognition signal 101 takes the significant value and theoperation of the timing controller 116 is reserved until a startingcondition is prepared.

The RAM monitor function is a function to read or rewrite contents ofthe RAM 140 and registers of the peripheral modules 1 and 2 inside theMCU 100 during the normal operation of the MCU 100, namely, during theoperation of the MCU 100 by an application program (hereinafter referredto as AP) which is written in the ROM 130.

In the case of reading data, in FIG. 1, when an address of a RAM oraddresses of registers, namely, the RAM 140, the peripheral module 1(150) and the peripheral module 2 (160) which are provided in the MCU100 and subjected to debugging are inputted from an external datainput/output terminal (hereinafter referred to simply as external datai/o terminal) in synchronization with an external clock from theexternal interface terminal group 102, necessary data is set in the DMAcontroller 110 by way of the data transmit/receive section 104. The DMAcontroller 110 reads data in the RAM or registers serving as objects ofset addresses by way of the internal bus, and outputs the read data tothe outside by way of the data transmit/receive section 104 and theexternal interface terminal group 102.

In the case of writing data, when an address of a RAM or addresses ofregisters, namely, the RAM 140, the peripheral module 1 (150) and theperipheral module 2 (160) which are provided in the MCU 100 andsubjected to debugging and data to be written are inputted from theexternal data i/o terminal in synchronization with the external clockfrom the external interface terminal group 102, necessary data is set inthe DMA controller 110 by way of the data transmit/receive section 104.The DMA controller 110 rewrites data stored in the RAM or registersserving as objects of set addresses by way of the internal bus, andoutputs a signal indicating the completion of execution of writing tothe outside by way of the data transmit/receive section 104 and theexternal interface terminal group 102.

However, in the conventional method, since a point (a state of programcounter (PC 121) inside the CPU 120) where the data in the RAM andregisters inside the MCU 100 are read or data is written on the RAM andregisters is a time upon completion of setting the DMA controller 110after setting data from the external interface terminal group 102, sucha point can not be set from the outside, causing a problem of lack offlexibility of debugging and another problem of low accuracy ofdebugging.

Under the circumstances, an on-chip debugging method of a MCU which isimproved in flexibility and accuracy of debugging has been desired.

SUMMARY OF THE INVENTION

In an on-chip debugging method of a MCU according to a first aspect ofthe invention, the MCU comprises an external interface terminal groupfor executing transmission and reception of data relative to an outside,a data transmit/receive section for executing transmission and receptionof data between the external interface terminal group and a DMAcontroller, the DMA controller having an address register for storingtherein an address of a hardware serving as an object to be accessed byDMA, registers for executing reading or writing by the DMA, a controlflag for controlling the start of the DMA, and a timing controller ofthe DMA. The MCU further includes outside thereof a register for storingtherein flag information for determining whether access can be executedor not by the DMA, and a unit for outputting a bus state recognitionsignal indicating whether a bus state of the MCU is in a state to beaccessed or not by the DMA, wherein when the flag information indicatesthat access can be executed by the DMA and the bus state recognitionsignal indicates that the bus can be occupied by the DMA, and thecontrol flag inside the DMA controller indicates that access is startedby the DMA, the built-in RAM or registers are accessed under the controlof the timing controller of the DMA inside the DMA controller so thatdata is read from the RAM or registers to the outside of the MCU or datais written to the RAM or registers from the outside.

In an on-chip debugging method of a MCU according to a second aspect ofthe invention, the MCU comprises an external interface terminal groupfor executing transmission and reception of data relative to an outside,a data transmit/receive section for executing transmission and receptionof data between the external interface terminal group and a DMAcontroller, the DMA controller having an address register for storingtherein an address of a hardware serving as an object to be accessed byDMA, a decoder for decoding a content of the address register, registersfor executing reading or writing by the DMA, a control flag forcontrolling the start of the DMA, and a timing controller of the DMA.The MCU further includes outside thereof a register for storing thereina DMA control flag group corresponding to each hardware one by one forexecuting access by the DMA, and a unit for outputting a bus staterecognition signal indicating whether a bus state of the MCU is in astate to be accessed or not by the DMA, wherein when a flag selectedfrom among the DMA control flag group in response to a signal outputtedby the decoder indicates that the DMA operation is valid, and the busstate recognition signal indicates that the bus can be occupied by theDMA, and the control flag inside the DMA controller indicates thataccess is started by the DMA, the built-in RAM or registers are accessedunder the control of the timing controller of the DMA inside the DMAcontroller so that data is read from the RAM or registers to the outsideof the MCU or data is written to the RAM or registers from the outside.

In an on-chip debugging method according to a third aspect of theinvention, the MCU comprises an external interface terminal group forexecuting transmission and reception of data relative to an outside, adata transmit/receive section for executing transmission and receptionof data between the external interface terminal group and a DMAcontroller; the DMA controller having an address register for storingtherein an address of a hardware serving as an object to be accessed byDMA, a register for inputting data indicating which flag of a DMAcontrol flag is referred to, a decoder for decoding a content of theregister, registers for executing reading or writing by the DMA, acontrol flag for controlling the start of the DMA, and a timingcontroller of the DMA. The MCU further includes outside thereof aregister for storing therein a DMA control flag group indicating whethereach hardware for executing access by the DMA can be accessed or not bythe DMA, and a unit for outputting a bus state recognition signalindicating whether a bus state of the MCU is in a state to be accessedor not by the DMA, wherein when a flag selected from among the DMAcontrol flag group in response to a signal outputted by the decoderindicates that the DMA operation is valid, and the bus state recognitionsignal indicates that access can be executed by the DMA, and the controlflag inside the DMA controller indicates that access is started by theDMA, the built-in RAM or registers are accessed under the control of thetiming controller of the DMA inside the DMA controller so that data isread from the RAM or registers to an outside of the MCU or data iswritten on the RAM or registers from the outside.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of the configuration of aconventional MCU;

FIG. 2 is a block diagram showing an on-chip debugging method accordingto a first embodiment of the invention;

FIG. 3 is a block diagram showing an on-chip debugging method accordingto a second embodiment of the invention; and

FIG. 4 is a block diagram showing an on-chip debugging method accordingto a third embodiment of the invention.

PREFERRED EMBODIMENTS OF THE INVENTION

Preferred embodiments of the invention are described hereinafter withreference to the attached drawings.

First Embodiment

FIG. 2 is a block diagram showing the configuration of a MCU 100according to a first embodiment of the invention. In FIG. 2, sincecomponents which are depicted by the same reference numerals as thoseillustrated in FIG. 1 have the same functions as those of the MCUillustrated in FIG. 1, a detailed explanation thereof is omitted.

In the first embodiment, a DMA control flag 170 is provided and it isnormally realized or formed of a flip—flip (F/F) and the like. A writesignal 171 is inputted to the DMA control flag 170 by an AP and the DMAcontrol flag 170 is arbitrarily set or reset by the AP. An output of theDMA control flag 170 is inputted to an AND gate 115 as one of threeinputs. The remaining two inputs of the AND gate 115 are the same asthose of the conventional MCU shown in FIG. 1.

(1) Reading Operation

An address of a RAM or addresses of registers, namely, the RAM 140, theperipheral module 1 (150) and a peripheral module 2 (160) which areprovided in the MCU 100 and subjected to debugging are inputted from anexternal data i/o terminal in synchronization with an external clockfrom the external interface terminal group 102 in FIG. 2, and datanecessary for the operation of the DMA controller 110 is set in an AReg112 by way of a data transmit/receive section 104. Upon completion ofthis setting process, a GO flag set F/F 111 is set. At this time, if abus state recognition signal has a significant value (e.g. a value “1”)and an output of the DMA control flag 170 set by the AP has asignificant value (e.g. a value “0”), the DMA controller 110 readscontent of the RAM or registers serving as objects of set addresses byway of a DBUS 106, and outputs the read data to the outside by way ofthe data transmit/receive section 104 and the external interfaceterminal group 102.

(2) Writing Operation

An address of a RAM or addresses of registers, namely, the RAM 140, theperipheral module 1 (150) and the peripheral module 2 (160) which areprovided in the MCU 100 and subjected to debugging and data to bewritten are inputted from the external data i/o terminal insynchronization with the external clock from the external interfaceterminal group 102, and data necessary for the operation of the DMAcontroller 110 is set in the Areg 112 and a WReg 113 by way of the datatransmit/receive section 104. Upon completion of this setting process,the GO flag set F/F 111 is set. At this time, if a bus state recognitionsignal has a significant value and an output of the DMA control flag 170set by the AP has a significant value, the DMA controller 110 writesdata on the RAM or registers serving as objects of set addresses by wayof the DBUS 106, and outputs a signal indicating the completion ofexecution of write to the outside by way of the external interfaceterminal group 102.

In the first embodiment, although the setting of data for executingread/write by the RAM monitor from the external interface terminal group102 is the same as the conventional method, there is provided the DMAcontrol flag 170 capable of programmably setting the set/reset by the APstored in the ROM 130, thereby controlling the operation of the DMAcontroller 110 so that the operation point of the DMA controller 110 isset by previously adding a program for controlling the state of the DMAcontrol flag 170 to the AP of the ROM 130. Accordingly, flexibility andaccuracy of debugging can be improved.

Second Embodiment

FIG. 3 is a block diagram showing the configuration of a MCU 100according to a second embodiment of the invention. Since componentswhich are depicted by the same reference numerals as those illustratedin FIGS. 1 and 2 have the same functions as those of MCU shown in FIGS.1 and 2, a detailed explanation thereof is omitted.

In the second embodiment, a DRAM control flag group 181 and a selector(SEL) 180 are provided outside the MCU 100 instead of the DMA controlflag 170 in the first embodiment. The DRAM control flag group 181 canset multiple flags in response to a command input 182 from the AP andeach flag corresponds one by one to an internal module of the RAM andthe like for executing read/write by a RAM monitor. For example, a RAM140 corresponds to a flag F0, a peripheral module 1 (150) corresponds toa flag F1, and a peripheral module 2 (160) corresponds to a flag F2.Flag information is inputted to an AND gate 115 by way of the SEL 180.

In the second embodiment, an address decoder (ADEC) 118 is providedinside the MCU 100 for decoding an address stored in an AReg 112, andoutputting a selection signal 119 for controlling the SEL 180.

(1) Reading Operation

An address of a RAM or addresses of registers, namely, the RAM 140, theperipheral module 1 (150) and the peripheral module 2 (160) which areprovided in the MCU 100 and subjected to debugging are inputted from anexternal data i/o terminal in synchronization with an external clockfrom the external interface terminal group 102, and data necessary forthe operation of a DMA controller 200 is set in an AReg 112 and thelike. Upon completion of this setting, a GO flag set F/F 111 is set. Atthis time, if a bus state recognition signal has a significant value anda value of an output signal of the SEL 180 selected in response to theselection signal from the ADEC 118 has a significant value (e.g. a value“1”), the DMA controller 200 outputs a read signal 123 to the RAM orregisters serving as objects to be read corresponding to set addressesand reads data in the RAM or registers and outputs the read data to theoutside by way of a timing controller 116, a RRreg 114, the datatransmit/receive section 104 and the external interface terminal group102.

At this time, the ADEC 118 decodes the address serving as an object ofthe RAM monitor and recognizes which hardware serving as an object ofthe RAM monitor the address in concern corresponds to and outputs asignal for selecting a flag of the DRAM control flag group 181 to beused to the selector SEL 180.

(2) Writing Operation

An address of a RAM or addresses of registers, namely, the RAM 140, theperipheral module 1 (150) and the peripheral module 2 (160) which areprovided in the MCU 100 and subjected to debugging and data to bewritten are inputted from the external data i/o terminal insynchronization with the external clock from the external interfaceterminal group 102, and data necessary for the operation of the DMAcontroller 200 is set in the AReg 112 and a WReg 113 by way of the datatransmit/receive section 104. Upon completion of this setting process, aGO flag is set, and at this time if a bus state recognition signal has asignificant value and a value of an output signal of the SEL 180selected in response to the selection signal 119 from the ADEC 118 has asignificant value, the DMA controller 200 outputs a write signal 122 tothe RAM or registers as objects to be written corresponding to setaddresses and writes data on the RAM or registers and outputs a signalindicating the completion of execution of writing to the outside by wayof the timing controller 116, the data transmit/receive section 104 andthe external interface terminal group 102.

In the second embodiment, since the DMA control flags are provided foreach module serving as an object of a RAM monitor, even if the debugpoint is differentiated for every module, the debugging accuracy can beimproved like the first embodiment.

Third Embodiment

FIG. 4 is a block diagram showing the configuration of a MCU 100according to a third embodiment of the invention. Since components whichare depicted by the same reference numerals as those illustrated inFIGS. 1, 2 and 3 have the same functions as those of MCU shown in FIGS.1, 2 and 3, a detailed explanation thereof is omitted.

A DMA controller 300 further includes, in addition to the components ofthe DMA controller 110 of the first embodiment, a DMA informationregister (Reg) 301 and a decoder (DEC) 302. The Reg 301 is a registerfor storing therein information relating to DMA inputted from anexternal interface terminal group 102, and this information indicateswhich information of DMA flag group is referred to.

(1) Reading Operation

In FIG. 4, address data of a RAM or registers, namely, a RAM 140, aperipheral module 1 (150), a peripheral module 2 (160), respectivelyserving as objects of debugging and DMA flag information data forspecifying which flag information is referred to among a DRAM controlflag group 181 are inputted to an external data i/o terminal insynchronization with an external clock of an external interface terminalgroup 102.

The inputted data is fetched such that the address data is fetched in anAReg 112, and DMA flag information data is fetched in a Reg 301, and theGO flag set F/F 111 for requesting reading operation by the RAM monitoris set at the same time upon completion of fetching of data.

The DMA controller 300 decodes the content of the DMA flag informationregister Reg 301 by the decoder DEC 302 and selects a flag to bereferred to among the DMA control flag group 181 by the SEL 180 inresponse to the decoded signal. Each flag among the DRAM control flaggroup 181 according to the third embodiment can freely set acorresponding relation relative to a hardware although the flagaccording to the second embodiment corresponds to a hardware one by one.For example, assuming that according to the second embodiment, the flagsF0, F1, F2 respectively correspond to the RAM 140, the peripheral module1 (150) and the peripheral module 2 (160), these flags can be changed torespectively correspond to the peripheral module 2 (160), the peripheralmodule 1 (150) and the RAM 140 by a hardware, not shown.

A timing controller 116 for controlling a reading operation by the RAMmonitor refers to states of three signals, i.e. a state of a Go flag, aselected DMA flag, and a bus state recognition signal 101 outputted froma CPU in the manner of in a hardware, and reserves the reading operationby the RAM monitor until these three signals are all set. If all thesignals are set, the timing controller 116 starts the reading operation,and outputs data stored in an AReg 112, to an internal address bus(ABUS) 108, and also outputs a data read signal 123.

Data in the RAM or registers serving as objects of reading by the RAMmonitor are outputted to an internal data bus DBUS 106 insynchronization with the read signal 123. The timing controller 116stores data outputted to the DBUS 106 in a RReg 114 and resets the GOflag set F/F 111. The content of thus stored RReg 114, namely, thecontent of the RAM or registers serving as objects of reading by the RAMmonitor are outputted to the outside by way of a data transmit/receivesection 104 and an external interface terminal group 102.

(2) Writing Operation

In FIG. 4, address data of a RAM or registers, namely, a RAM 140, aperipheral module 1 (150), a peripheral module 2 (160), respectivelyserving as objects of debugging, write data and DMA flag informationdata for specifying which flag information is referred to among a DRAMcontrol flag group 181 are inputted to an external data i/o terminal insynchronization with an external clock of an external interface terminalgroup 102.

Each inputted data is fetched such that an address data is fetched inthe AReg 112, write data is fetched in the WReg 113, DMA flaginformation data is fetched in the DMA flag information register Reg301, and the GO flag set F/F 111 for requesting reading operation by theRAM monitor is set at the same time upon completion of fetching of data.

The DMA controller 300 decodes the content of the DMA flag informationregister Reg 301 by the decoder DEC 302 and selects a flag to bereferred to among the DMA control flag group 181 by the SEL 180 inresponse to the decoded signal. The relation between each flag of thecontrol flag group 181 and each hardware according to the thirdembodiment can be varied in the same manner as mentioned above.

A timing controller 116 for controlling a writing operation by the RAMmonitor refers to states of three signals, i.e. a state of a Go flag, aselected one DMA flag, a bus state recognition signal 101 outputted froma CPU in the manner of in a hardware and reserves the writing operationby the RAM monitor until these three signals are all set. If all thesignals are set, the timing controller 116 starts the writing operation,and outputs data stored in an AReg 112, to an internal address bus(ABUS) 108, and also outputs a data write signal 122.

Data in the RAM or registers serving as objects of writing by the RAMmonitor are outputted to a hardware serving as an object from theinternal data bus DBUS 106 in synchronization with the write signal 122.The timing controller 116 resets the GO flag set F/F 111 upon completionof writing operation and outputs the completion of execution of writingto the outside by way of the data transmit/receive section 104 and theexternal interface terminal group 102.

According to the RAM monitor in the third embodiment, since the DMAcontrol flags which are referred to by the RAM or registers serving asobjects of monitor can be individually set, a debugging point which isfiner than those of first and second embodiments can be set, therebyimproving the efficiency of debugging.

1. A microcontroller provided with a function of reading from or writingto a built-in RAM or registers during execution of an applicationprogram, wherein said microcontroller comprises: an external interfaceterminal group for executing transmission and reception of data relativeto an outside; and a data transmit/receive section for executingtransmission and reception of data between the external interfaceterminal group and a DMA controller; wherein the DMA controller includesan address register for storing therein an address of a hardware servingas an object to be accessed by DMA, registers for executing reading orwriting by the DMA, a control flag for controlling the start of the DMA,and a timing controller of the DMA; wherein said microcontroller iscoupled externally to a register for storing therein flag informationfor determining whether access can be executed or not by the DMA, and aunit for outputting a bus state recognition signal indicating whether abus state of the microcontroller is in a state to be accessed or not bythe DMA; and wherein, when (1) the flag information indicates thataccess can be executed by the DMA, (2) the bus state recognition signalindicates that the bus can be occupied by the DMA, and (3) the controlflag inside the DMA controller indicates that access is started by theDMA, the built-in RAM or registers are accessed under the control of thetiming controller of the DMA inside the DMA controller so that data isread from the RAM or registers to the outside of the microcontroller ordata is written to the RAM or registers from the outside.
 2. Amicrocontroller provided with a function of reading from or writing to abuilt-in RAM or registers during execution of an application program,wherein said microcontroller comprises: an external interface terminalgroup for executing transmission and reception of data relative to anoutside; and a data transmit/receive section for executing transmissionand reception of data between the external interface terminal group anda DMA controller; wherein the DMA controller includes an addressregister for storing therein an address of a hardware serving as anobject to be accessed by DMA, a decoder for decoding a content of theaddress register, registers for executing reading or writing by the DMA,a control flag for controlling the start of the DMA, and a timingcontroller of the DMA; wherein said microcontroller is coupledexternally to a register for storing therein a DMA control flag groupcorresponding to each hardware one by one for executing access by theDMA, and a unit for outputting a bus state recognition signal indicatingwhether a bus state of the microcontroller is in a state to be accessedor not by the DMA; and wherein, when (1) flag selected from among theDMA control flag group in response to a signal outputted by the decoderindicates that a DMA operation is valid, (2) the bus state recognitionsignal indicates that the bus can be occupied by the DMA, and (3) thecontrol flag inside the DMA controller indicates that access is startedby the DMA, the built-in RAM or registers are accessed under the controlof the timing controller of the DMA inside the DMA controller so thatdata is read from the RAM or registers to the outside of themicrocontroller or data is written to the RAM or registers from theoutside.
 3. A microcontroller provided with a function of reading fromor writing to a built-in RAM or registers during execution of anapplication program, wherein said microcontroller comprises: an externalinterface terminal group for executing transmission and reception ofdata relative to an outside; and a data transmit/receive section forexecuting transmission and reception of data between the externalinterface terminal group and a DMA controller; wherein the DMAcontroller includes an address register for storing therein an addressof a hardware serving as an object to be accessed by DMA, a register forinputting data indicating which flag of a DMA control flag is referredto, a decoder for decoding a content of the register, registers forexecuting reading or writing by the DMA, a control flag for controllingthe start of the DMA, and a timing controller of the DMA; wherein saidmicrocontroller is coupled externally to a register for storing thereina DMA control flag group indicating whether each hardware for executingaccess by the DMA can be accessed or not by the DMA, and a unit foroutputting a bus state recognition signal indicating whether a bus stateof the microcontroller is in a state to be accessed or not by the DMA;and wherein, when (1) a flag selected from among the DMA control flaggroup in response to a signal outputted by the decoder indicates thatthe DMA operation is valid, (2) the bus state recognition signalindicates that access can be executed by the DMA, and (3) the controlflag inside the DMA controller indicates that access is started by theDMA, the built-in RAM or registers are accessed under the control of thetiming controller of the DMA inside the DMA controller so that data isread from the RAM or registers to an outside of the microcontroller ordata is written on the RAM or registers from the outside.